1. Field of the Invention
This invention relates generally to methods and circuit configurations for measuring response delay times of integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that boast superior speed performance. This, in turn, leads IC manufacturers to carefully test the speed performance of their designs.
FIG. 1A (prior art) shows a bus structure 100 in which three tri-state buffers 105, 110, and 115 alternatively drive a bus line 117. A control circuit 120 selectively enables one of the three tri-state buffers to connect one of signal lines DAT0, DAT1, and DAT2 to line 117. The de-selected selected tri-state buffers offer a high impedance to bus line 117, and consequently do not interfere with transmitted signals.
Bus structure 100 is useful for external communication (bus line 117 connects to external devices) in which disabled tri-state buffers driving a bus line have to be tri-stated, but is uneconomical and consumes a considerable amount of die area when implemented within the fabric of an IC for internal communication. Circuit designers have therefore developed smaller, more economical substitutes for bus structure 100.
FIG. 1B (prior art) is a multiplexer chain 150 that implements the function of bus structure 100 of FIG. 1A without some of the drawbacks. Multiplexer chain 150 includes first, intermediate, and last multiplexers 160, each having a first multiplexer input IN0, a second multiplexer input IN1, and a multiplexer control terminal SEL selecting which of the multiplexer inputs is connected to a multiplexer output terminal OUT. The output of the first multiplexer connects to the input IN0 of the intermediate multiplexer via an interconnect B0 and the output of the intermediate multiplexer connects to input IN1 of the final multiplexer via an interconnect line B1. The second input IN1 of each multiplexer connects to a respective one of data terminals DAT0 DAT1, and DAT2; the select terminals SEL connect to a control circuit 170 via respective enable lines EN0, EN1, and EN2. Applying appropriate control signals to multiplexers 160, control circuit 170 connects one of data terminals DAT0-2 to an interconnect line B2, the output of the last multiplexer.
Chain 150 is functionally similar to bus structure 100 of FIG. 1A, passing only one data signal at a time to avoid contention. Taking terms borrowed from tri-state buffers, an “enabled” multiplexer transmits the input signal on its respective input terminal IN1, while a “disabled” multiplexer transmits the input signal on its respective input terminal IN0. Disabling all of multiplexers 160 connects an input terminal 165 to interconnect B2, whereas enabling any one of multiplexers 160 connects the respective one of data terminals DAT0-2, to interconnect B2. For more information and detail on how multiplexer chain 150 implements bus structure 100, see U.S. Pat. No. 5,847,580 issued to Bapat et al.
When multiplexer chain 150 is used in high-speed systems requiring very low timing tolerances, the time required for the multiplexers to switch between enabled and disabled states becomes a critical component of the timing parameters of multiplexer chain 150. There is therefore a need for a way to characterize the speed performance of multiplexer chain 150 and similar circuits.
Among the myriad types of ICs, perhaps none requires more stringent speed characterization than field-programmable gate arrays (FPGAs). As is well known, FPGAs include various types of programmable logic and interconnect resources that can be programmably interconnected to form complex, user-specified designs. FPGA designers use “speed files” that include resistance and capacitance values for the various delay-inducing elements and combine them to establish delays for desired signal paths. These delays are then used to predict circuit timing for selected circuit designs implemented as FPGA configurations. FPGA timing parameters are assigned worst-case values to ensure FPGA designs work as indicated.
FPGA manufacturers would like to guarantee the highest speed performance possible without causing ICs to fail to meet the guaranteed timing specifications. More accurate measurements of circuit timing allow IC designers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate means of characterizing IC speed performance.
Recent advances in IC test methodologies, particularly important in the field of programmable logic, employ ring oscillators to characterize speed performance. In general, a number of components are configured in a loop so they together form a free-running ring oscillator. The oscillation period of the oscillator is then a measure of the combined delays through the oscillator's constituent components. Different oscillator configurations have been developed to characterize different circuit features, different circuit parameters, and the effects of different types of signal edges (e.g., rising vs. falling signal transitions). For an example of a ring-oscillator configuration that measures some forms of signal propagation delays in FPGAs, see U.S. Pat. No. 6,075,418 issued to Kingsley et al., which is incorporated herein by reference.
Oscillator test configurations work well to characterize speed performance, but have not been adapted for use with some important types of circuit configurations. They have not been applied, for example, to multiplexer chain 150 described above in connection with FIG. 1B. As a consequence, there remains a need for a means of precisely characterizing some forms of multi-input combinatorial logic circuits, including multiplexer chain 150.